This invention is in the field of integrated circuit test and evaluation, and is more specifically directed to test and analysis of operating margins in solid-state memories.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM memory cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
Advances in semiconductor technology in recent years have enabled shrinking of minimum device feature sizes (e.g., MOS transistor gates) into the sub-micron range. This miniaturization is especially beneficial when applied to memory arrays, because of the large proportion of the overall chip area often devoted to on-chip memories. As a result, significant memory resources are now often integrated as embedded memory into larger-scale integrated circuits, such as microprocessors, digital signal processors, and “system-on-a-chip” integrated circuits. However, this physical scaling of device sizes raises significant issues, especially in connection with embedded SRAM memory but also in SRAM memory realized as “stand-alone” memory integrated circuit devices. Several of these issues are due to increased variability in the electrical characteristics of transistors formed at these extremely small feature sizes. This variability in characteristics has been observed to increase the likelihood of read and write functional failures, on a cell-to-cell basis. Sensitivity to device variability is especially high in those memories that are at or near their circuit design limits. The combination of increased device variability with the larger number of memory cells (and thus transistors) within an integrated circuit renders a high likelihood that one or more cells cannot be read or written as expected.
These failure mechanisms include, among others, cell stability failures, write failures, and read failures. In a general sense, a cell stability failure occurs when an unaddressed SRAM cell changes state, for example as a result of an access to a neighboring cell that disturbs the unaddressed cell sufficiently to cause its stored data state to “flip”. A write failure occurs when an addressed SRAM cell does not change its stored state when written with the opposite data state, and a read failure occurs when an addressed cell fails to communicate a sufficiently strong signal indicative of its stored state.
These various failure mechanisms will now be described in further detail in connection with an example of a conventional SRAM cell, referring to FIG. 1a. In this example, SRAM cell 12 of FIG. 1a is a conventional six-transistor (6-T) static memory cell 12, which in this case is in the jth row and kth column of a memory array. SRAM memory cell 12 is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 12 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel transistor 13p and n-channel transistor 13n, and the other inverter of series-connected p-channel transistor 14p and n-channel transistor 14n; the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. The common drain node of transistors 13p, 13n constitutes storage node SNT, and the common drain node of transistors 14p, 14n constitutes storage node SNB, in this example. N-channel pass transistor 15a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass transistor 15b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass transistors 15a, 15b are driven by word line WLj for this jth row in which cell 12 resides.
In operation, bit lines BLTk, BLBk are typically precharged to a high voltage (at or near power supply voltage Vdda), and are equalized to the same voltage. To access cell 12 for a read operation, word line WLj is then energized, turning on pass transistors 15a, 15b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. The differential voltage developed on bit lines BLTk, BLBk is then sensed and amplified by a sense amplifier. In a write operation, typical modern SRAM memories include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 12 to latch in the desired state.
Cell stability refers to the ability of SRAM cell 12 to withstand static noise without changing states. A quantitative measure of cell stability is referred to in the art as static noise margin, which corresponds to the noise at a storage node that the cell can tolerate without changing its logic state. FIG. 1b graphically illustrates the concept of static noise margin for cell 12 of FIG. 1a. In FIG. 1b, the storage node voltages VSNT, VSNB are plotted against one another. Curve TF1-0 represents the transfer function of the storage node voltages VSNT, VSNB for a transition of cell 12 from a “1” data state to a “0” data state (i.e., storage node SNT changing state from high to low). Conversely, curve TF0-1 represents the transfer function for the opposite data transition. The two stable points STR1, STR0 represent the operating points at which a relatively stable cell 12 resides in the “1” and “0” data states, respectively; these points STR1, STR0 are stable in the sense that the storage node voltages VSNT, VSNB will return to these points after small voltage variations. Metastable operating point VXSTR is at the crossing point of the two transfer function curves TF0-1, TF1-0, with a storage node SNT voltage VMSTR; this operating point VXSTR can serve as a balanced indeterminate logic state, but is metastable in the sense that a small variation in voltage at either storage node would cause cell 12 to flip to one of the stable logic states. For this stable cell 12, with operating points STR1, STR0, the static noise margin for the “1” state is represented by the size of square SNMSTR; a similar square is defined for the “0” state, as shown in FIG. 1b. 
The transfer functions of a weak cell are also shown in FIG. 1b. For the sake of clarity of this description, this weak, or unstable, cell 12 has a “1” state operating point WK1 (its “0” state operating point STR0 is the same as described above, in this example). This operating point WK1 indicates that storage node SNB is not strongly pulled toward ground Vssa by transistor 14n. As known in the art, this condition is due to such physical causes as transistor drive mismatch within cell 12, for example resulting in transistor 14p (operating in its saturated regime due to the high level at its gate voltage) pulling storage node SNB toward power supply voltage Vdda. This shifts the transfer function for this weak cell 12, as shown by curve TF*1-0 in FIG. 1b. The static noise margin for this weak “1” cell is smaller than that for the strong cell, as evident by smaller square SNMWK shown in FIG. 1b. As a result, metastable operating point VXWK at the crossing point of the transfer function curves TF*1-0, TF0-1 is at a higher storage node SNT voltage VMWK than voltage VMSTR of metastable operating point VXSTR, reflecting that the cell will change state from “1” to “0” at a higher bit line voltage than will a strong cell.
A conventional cell stability test is performed by setting cell 12 to a known state, then applying a disturb voltage to one of its storage nodes, and then determining whether a change of stored state resulted. For example, referring to FIG. 1b, cell 12 is first set into a “1” state (storage node SNT at a “1” level), following which a disturb voltage is applied to storage node SNT, pulling that node voltage down to voltage VTEST. If cell 12 is a stable cell, for example with static noise margin SNMSTR as shown in FIG. 1b, a storage node voltage VSNT=VTEST is above metastable voltage VMSTR of operating point VXSTR. Cell 12 would return to operating point STR1 in this event, despite the disturb voltage. Conversely, if cell 12 is relatively unstable, for example with static noise margin SNMWK as shown in FIG. 1b, a storage node voltage VSNT=VTEST is below metastable voltage VMWK. In this case, cell 12 would “flip” logic states, settling to operating point STR0 as a result. In this case, the disturb voltage at storage node SNT causes cell 12 to lose its data state.
Of course, it is difficult to apply such a disturb voltage directly to storage nodes of SRAM cells in actual SRAM memories, and cumbersome to provide the necessary internal conductors within the memory to do so. One conventional approach to performing such a cell stability test implements a “weak write” special test mode in the memory. This approach is described in Meixner et al., “Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique”, Proc. IEEE Int. Test Conf. (November 1997), pp. 1043-52. However, as described in this paper, this test method requires implementation of special “weak” write circuits in the memory itself, which will of course be redundant with the normal memory write circuits and thus require additional chip area for the circuits and associated control and data conductors.
Another cell stability test is described in Pavlov et al., “Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique”, J. Solid State Circ., Vol. 41, No. 10 (IEEE, October 2006), pp. 2334-43. In this approach a cell under test is written to a known data state. Other cells in its same column (i.e., that share the same bit line pairs) are written, with the ratio n of their data states corresponding to the ratio of these same-column cells that receive an opposite data state from that of the cell under test, to those that receive the same data state. Bit line precharge is then disabled, and the word lines of the written disturb cells are simultaneously energized, discharging the bit line according to the data ratio n. The word line of the cell under test is then pulsed, to transfer the “disturb” voltage now present on the bit lines to the storage nodes of the cell under test. A read of the cell under test determines whether the disturb voltage upset the previously stored data state. However, it is believed that the simultaneous energizing of multiple word lines in a memory array requires a large amount of switching power to be provided to, and by, row decoders and word line drive circuits. While this power consumption would be required only in device test, the conductors and drive circuits involved in driving multiple word lines must be designed and constructed accordingly, involving additional chip area.
Other conventional tests for cell stability include reducing the power supply voltage (i.e., power supply voltage Vdda in FIG. 1a) while maintaining normal peripheral circuit bias, and then operating the memory. Another stability test involves performing “long” writes to some cells in the array, to determine whether other cells were disturbed.
Write failures in SRAM memories occur when the SRAM cell does not properly switch its stored state in a write operation. Typically, this failure has been observed to be due to the inability of write circuitry to pull down the storage node currently latched to a high voltage. For example, referring to FIG. 1a, beginning from a state in which storage node SNT is at a “1” and storage node SNB is at a “0”, the writing of a “0” state will be performed by bit line BLTk being pulled low, and connected to storage node SNT by pass transistor 15a, while the precharged (Vdda) voltage is applied to storage node SNB via pass transistor 15b. The write of cell 12 thus depends on the ability of these bit line voltages to counteract the drive of transistors 13p, 14n. If device imbalances within cell 12 prevent the “flipping” of its state, the write operation will fail and storage node SNT will remain latched at a high level despite the attempted write. In this sense, therefore, write failures are the converse of cell stability failures—a write margin failure occurs if a cell is too stubborn in changing its state, while a cell stability failure occurs if a cell changes its state too easily.
A read failure occurs if the SRAM cell provides insufficient current to the bit lines when accessed. Referring to FIG. 1a by way of example, the data state stored in cell 12 is communicated to bit lines BLTk, BLBk upon word line WLj being energized to turn on pass transistors 15a, 15b, after bit lines BLTk, BLBk are precharged to a high voltage. The one of storage nodes SNT, SNB that is latched to a low logic level pulls its corresponding bit line BLTk, BLBk low, with a read current constituted by the one of transistor pairs (i.e., transistors 15a and 13n, or transistors 15b and 14n) that is turned on, establishing a differential bit line voltage. Device imbalances and the like can cause weakness in the drive by that n-channel pass gate/drive transistor pair, for example if the opposing p-channel transistors 13p, 14p only weakly turns on the cross-coupled n-channel drive transistors 14n, 13n, respectively, in its latched state.